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1 12-bit, 20ksps sar adc ISL2671286 the ISL2671286 is a sampling sar-type adc which features excellent linearity over supply and temperature variations, and provides a drop-in compatible alternative to all ads1286 performance grades. the robust high impedance input minimizes errors due to leakage currents, and specified measurement accuracy is maintained with input signals up to the supply rails. the reference accepts inputs between 1.25v to 5.0v, providing design flexibility in a wide variety of applications. the ISL2671286 also features up to 8kv human body model esd survivability. the serial digital interface is spi compatible and is easily interfaced to all popular fpgas and microcontrollers. operating from a 5v supply, po wer dissipation is 1.4mw at a sampling rate of 20ksps and just 15w between conversions utilizing the auto power-down mode. these features make the ISL2671286 an excellent solution for remote industrial sensors and battery-powered instruments. the ISL2671286 is available in an 8 ld soic package and is specified for operation over the industrial temperature range of ?40c to +85c. features ? drop-in compatible with ads1286 (all performance grades) ? simple spi-compatible serial digital interface ? guaranteed no missing codes ? 20khz sampling rate ? +4.50v to +5.25v supply ? low 280a operating current (20ksps) ? power-down current between conversions: 3a ? excellent differential no n-linearity (0.75lsb max) ? low thd: -83db (typ) ? pb-free (rohs compliant) ? available in soic package applications ? remote data acquisition ? battery operated systems ? industrial process control ? energy measurement ? data acquisition systems ? pressure sensors ? flow controllers figure 1. block diagram figure 2. diff erential linearity error vs code serial interface +vcc vref gnd +in ? in dclock dout cs/shdn dac dac sar logic vref -3 -2 -1 0 1 2 3 0 512 1024 1536 2048 2560 3072 3584 4096 code differential nonlinearity (lsb) november 1, 2011 fn7863.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL2671286 2 fn7863.0 november 1, 2011 typical connection diagram pin configuration ISL2671286 (8 ld soic) top view + vref +in ?in gnd +vcc dclock dout cs/shdn ref p-p + + +5v supply p/ c vref serial interface 10 f 0.1 f vref 8 7 6 5 1 2 3 4 +in ? in gnd +vcc dclock dout cs/shdn pin descriptions pin name pin number description vref 1 reference input +in 2 non-inverting input ?in 3 inverting input. connect to ground or remote sense point. gnd 4 ground cs /shdn 5 chip select when lo w; shut-down mode when high. dout 6 serial output data wo rd comprises 12 bits of data. in operation, data is valid on falling edge of dclock. second clock pulse after falling edge of cs /shdn enables serial output. after one null bit, data is valid for next 12 edges. dclock 7 data clock synchronizes serial data transfer. +vcc 8 power supply ordering information part number (notes 1, 2) part marking +vcc range (v) temp range (c) package pkg. dwg. # ISL2671286ibz (note 3) 2671286 ibz 4.50 to 5.25 -40c to +85c 8 ld soic m8.15 coming soon ISL2671286ipz 2671286 ipz 4.50 to 5.25 -40c to +85c 8 ld pdip e8.3 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL2671286 . for more information on msl please see tech brief tb363 .
ISL2671286 3 fn7863.0 november 1, 2011 absolute maximum rating s thermal information any pin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v analog input to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to +vcc+0.3v digital i/o to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to +vcc+0.3v external reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6v maximum current in to any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 8kv machine model (tested per jesd22-a115b) . . . . . . . . . . . . . . . . . 400v charged device model (tested per jesd22-c101e). . . . . . . . . . . . .1.5kv latch up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld soic package (notes 4, 5). . . . . . . . . . 120 64 8 ld pdip package (notes 5, 6, 7) . . . . . . . 120 66 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+100c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. 6. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. pb-free pdips can be used for through hole wave solder processi ng only. they are not intended for use in reflow solder proces sing applications. electrical specifications +vcc = +5v, v ref = +5v, f sample = 12.5khz, f clk =16 ? f sample , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 8) typ max (note 8) units analog input (note 9) |ain| full-scale inpu t range +in ? (?in) 0vref v absolute input voltage +in -0.2 +vcc +0.2 v ?in -0.2 +0.2 v c in input capacitance track/hold mode 19/1.8 pf i leak input dc leakage current (note 10) -1 0.01 1 a system performance nresolution 12 bits no missing codes guaranteed no missed codes 12 bits inl integral linearity -1 0.5 1 lsb dnl differential linearity -0.75 0.4 0.75 lsb offset zero-code error -3 0.1 3 lsb gain gain error -8 0.2 8 lsb psrr power supply rejection 82 db sampling dynamics t conv conversion time 12 clk cycles t acq acquisition time 1.5 clk cycles ssbw small signal bandwidth 320 khz dynamic characteristics thd total harmonic distortion ain = 5.0v pp at f in = 1khz -82 db ain = 5.0v pp at f in = 5khz -83 db sinad signal-to (noise + distortion) ratio ain = 5.0v p-p at f in = 1khz 72 db sfdr spurious free dynamic range ain = 5.0v p-p at f in = 1khz 83 db
ISL2671286 4 fn7863.0 november 1, 2011 reference input ref ref input range 1.25 2.5 vcc + 0.05 v refleak current drain cs /shdn = vcc -2.5 0.01 2.5 a t cyc 640s, f clk 25khz 0.06 20 a t cyc = 80s, f clk = 200khz 0.5 20 a digital input/output logic family cmos v ih input high voltage 3+vcc v v il input low voltage 0.0 0.8 v v oh output high voltage i oh = 250a 3+vcc v v ol output low voltage i ol = 250a 0.0 0.4 v data format straight binary i leak input dc leakage current -1 0.01 1 a c in input capacitance 9pf i oz floating-state output leakage current -1 0.01 1 a c out floating-state output capacitance 6 pf power supply requirements +vcc power supply voltage 4.50 5 5.25 v v ana quiescent current t cyc 640s, f clk 25khz 280 500 a t cyc = 90s, f clk = 200khz 360 600 a power down cs /shdn = vcc 0.5 3 a temperature range specified performance -40 +85 c notes: 8. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 9. the absolute voltage applied to each analog input must be between gnd and +vcc to guarantee datasheet performance. 10. applies only to +in. electrical specifications +vcc = +5v, v ref = +5v, f sample = 12.5khz, f clk =16 ? f sample , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 8) typ max (note 8) units timing specifications at f clk = 200khz , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 8) typ max (note 8) units t smpl analog input sample time see operating sequence; figure 3 1.5 2.0 clk cycles t smpl (max) maximum sampling frequency 20 khz t conv conversion time see operating sequence; figure 3 12 clk cycles t ddo delay time, dclock to dout data valid see test circuits; figure 4 36 150 ns t dis delay time, cs /shdn to dout hi-z see test circuits; figure 4 (note 11) 50 ns t en delay time, dclock to dout enable see test circuits; figure 4 21 100 ns
ISL2671286 5 fn7863.0 november 1, 2011 t hdo output data remains valid after dclock cload = 100pf 15 30 ns t f dout fall time see test circuits; figure 4 1 100 ns t r dout rise time see test circuits; figure 4 1 100 ns t csd delay time, cs /shdn to dclock see operating sequence; figure 3 0 ns t sucs delay time, cs /shdn to dclock see operating sequence; figure 3 30 ns note: 11. during characterization, t dis is measured from the release point with a 10pf load (s ee figure 4) and the equivalent timing using the ads1286 loading (3k ? , 100pf) is calculated. timing specifications at f clk = 200khz , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 8) typ max (note 8) units figure 3. serial interface timing diagram t sucs b10b9b8b7b6b5b4b3b2b1b0 b11b10b9b8 null bit hi-z hi-z null bit cs/shdn dclock dout t csd t cyc power down t smpl t conv t data note: (1) after completing the data transfer, additional clocks applied while cs/shdn is low will result in the previous data being retransmitted lsb-first, followed by indefinite transmission of zeros t sucs b10b9b8b7b6b5b4b3b2b1b0 b11 b10 b9 b8 null bit hi-z hi-z cs/shdn dclock dout t csd t cyc power down t smpl t conv t data note: (2) after completing the data transfer, additional clocks applied while cs/shdn is low will result in indefinite transmission of zeros b1 b2 b3 b4 b5 b7 b6 b11 (msb) b11 (msb) (1) (2) figure 4. equivalent load circuit output pin c l 10pf +vcc 2.85k r l
ISL2671286 6 fn7863.0 november 1, 2011 50% t en vol = 0.4v dout dclock vil = 0.8v t hdo voh = vdd - 0.2v dout dclock t sucs 50% dclock cs /shdn 50% 50% t csd 50% cs /shdn dclock t hdo vil = 0.8v vol = 0.4v dclock dout cs /shdn dout vih = 2.4v t dis 10% figure 5. timing parameter definitions
ISL2671286 7 fn7863.0 november 1, 2011 typical performance characteristics at t a = +25c, +vcc = v ref = 5v, f sample = 12.5khz, f clk = 16 * f sample , unless otherwise specified. figure 6. reference current vs sample rate figure 7. reference current vs temperature figure 8. change in offset vs reference volt age figure 9. change in offset vs temperature figure 10. change in integral linearity and differential linearity vs reference voltage figure 11. change in gain vs reference voltage 0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 sample rate (khz) reference current (a) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -55 -35 -15 5 25 45 65 85 105 temperature (c) reference current (a) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 reference voltage (v) change in offset (lsb) 1 2 3 4 5 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -55 -35 -15 5 25 45 65 85 105 temperature (c) delta from 25c (lsb) -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 change in dnl (lsb) change in inl (lsb) 1 2 3 4 5 reference voltage (v) delta from +5v reference (lsb) -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 1 2 3 4 5 reference voltage (v) change in gain (lsb)
ISL2671286 8 fn7863.0 november 1, 2011 figure 12. effective number of bi ts vs reference voltage figure 13. d ifferential linearity error vs code figure 14. signal-to-(noise + distortion) vs freq uency figure 15. spurious free dynamic range and signal-to-noise ratio vs frequency figure 16. signal-to-(noise + distortion) vs input leve l figure 17. total harmonic distortion vs frequency typical performance characteristics at t a = +25c, +vcc = v ref = 5v, f sample = 12.5khz, f clk = 16 * f sample , unless otherwise specified. (continued) 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 0.1 1.0 10.0 reference voltage (v) effective number of bits (bits) -3 -2 -1 0 1 2 3 0 512 1024 1536 2048 2560 3072 3584 4096 code differential nonlinearity (lsb) 0 10 20 30 40 50 60 70 80 90 100 frequency (khz) 0.1 1.0 10.0 signal-to-(noise + distortion) (db) 0 10 20 30 40 50 60 70 80 90 100 spurious free dynamic range signal-to-noise ratio frequency (khz) 0.1 1.0 10.0 sfdr and snr (db) 0 10 20 30 40 50 60 70 80 -40 -35 -30 -25 -20 -15 -10 -5 0 input level (db) signal-to-(noise + distortion) (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 frequency (khz) 0.1 1.0 10.0 total harmonic distortion (db)
ISL2671286 9 fn7863.0 november 1, 2011 figure 18. 4096 point fft figure 19. powe r supply rejection vs ripple frequency figure 20. change in gain vs temperature figure 21. power-down supply current vs temperature figure 22. supply current vs temperature f igure 23. integral linearity error vs code typical performance characteristics at t a = +25c, +vcc = v ref = 5v, f sample = 12.5khz, f clk = 16 * f sample , unless otherwise specified. (continued) -125 -100 -75 -50 -25 0 0 2 4 6 frequency (khz) magnitude (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1 10 100 1k 10k ripple frequency (khz) power supply rejection (db) -0.50 -0.25 0.00 0.25 0.50 -55 -35 -15 5 25 45 65 85 105 temperature (c) delta from 25c (lsb) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -55 -35 -15 5 25 45 65 85 105 temperature (c) supply current (a) 100 150 200 250 300 350 400 450 f sample = 12.5khz f sample = 1.6khz -55 -35 -15 5 25 45 65 85 105 temperature (c) supply current (a) -3 -2 -1 0 1 2 3 0 512 1024 1536 2048 2560 3072 3584 4096 code integral nonlinearity (lsb)
ISL2671286 10 fn7863.0 november 1, 2011 figure 24. digital input line threshold vs supply vo ltage figure 25. input leakage current vs temperature typical performance characteristics at t a = +25c, +vcc = v ref = 5v, f sample = 12.5khz, f clk = 16 * f sample , unless otherwise specified. (continued) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 supply voltage (v) digital input threshold voltage (v) 0.01 0.1 1.0 10.0 -55 -35 -15 5 25 45 65 85 105 temperature (c) leakage current (na)
ISL2671286 11 fn7863.0 november 1, 2011 functional description the ISL2671286 is based on a su ccessive approximation register (sar) architecture utilizing capacitive charge redistribution digital-to-analog converters (dacs) . figure 26 shows a simplified representation of the converter. during the acquisition phase (acq), the differential input is stored on the sampling capacitors (cs). the comparator is in a balanced state since the switch across its inputs is closed. the si gnal is fully acquired after t acq has elapsed, and the switches then transition to the conversion phase (conv) so the stored voltage can be converted to digital format. the comparator beco mes unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltag e is not exactly at mid-scale). the comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the msb. the sar logic then forces the capacitive dacs to adjust up or down by one-quarter of full-scale by sw itching in binarily weighted capacitors. again, the comparator output reflects whether the stored voltage is above or below the new value and sets the value of the next lowest bit. this proc ess repeats until all 12 bits have been resolved. adc transfer function the output coding for the ISL2671286 is straight binary. the first code transition occurs at succe ssive lsb values (i.e., 1 lsb, 2 lsb, and so on). the lsb size is vref/4096. the ideal transfer characteristic of the ISL2671286 is shown in figure 27. analog input the ISL2671286 features a pseudo-differential input with a nominal full-scale range equal to the applied vref voltage. the negative input (vin?) must be biased within 200mv of ground. modes of operation there are two possible modes of operation, which are controlled by the cs /shdn signal. when cs /shdn is high (deasserted), the adc is in static mode. conversely, when cs /shdn is low (asserted), the device is in dynamic mode. there is no minimum or maximum number of sclk cycles required to enter static mode. this simplifies power management and allows the user to easily optimize power dissipation versus throughput for various application requirements. dynamic mode this mode is entered when a co nversion result is desired by asserting cs /shdn. figure 28 shows the general operation in this mode. the conversion is initiated on the falling edge of cs /shdn (refer to ?serial digital interface? section). when cs /shdn is deasserted, the conversion is terminated, and dout returns to a high-impedance state. sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. cs /shdn may idle high until the next conversion or idle low until sometime prior to the next conversion. once a data transfer is complete (dout has returned to a high-impedance state), another conversion can be initiated by again asserting cs /shdn. standby mode the ISL2671286 enters the power-saving static mode automatically any time cs /shdn is deasserted. the user is not required to force a device into this mode following a conversion in order to optimize power consumption. short cycling in cases where a lower resoluti on conversion is acceptable, cs /shdn can be pulled high before 12 sclk falling edges have elapsed. this is referred to as short cycling, and it can be used to further optimize power dissipation. in this mode, a lower resolution result is acquired, but the adc enters static mode sooner and exhibits a lower averag e power dissipation than if the complete conversion cycle is ca rried out. the acquisition time ( t acq ) requirement must be met for the next conversion to be valid. power-on reset the ISL2671286 performs a power-on reset that requires approximately 2.5ms to execute when the supplies are first figure 26. sar adc architectural block diagram vin+ vin ? vref acq conv acq acq conv conv dac dac sar logic 1lsb = vref/4096 000...000 000...001 000...010 011...111 100...000 100...001 111...110 111...111 adc code analog input +in ?(?in) +?lsb +vref ? 1?lsb 0v +vref ? 1lsb figure 27. ideal tran sfer characteristics sclk dout csb 10 116 4 leadi ng zeros and conversi on result figure 28. normal mode operation
ISL2671286 12 fn7863.0 november 1, 2011 activated. after reset is complete, a single dummy cycle lasting one conversion must be executed to initialize the switched capacitor track and hold. once the dummy cycle is complete, the adc mode is determined by the state of cs /shdn. at this point, switching between dynamic and static modes is controlled by cs /shdn, with no delay required between states. power vs throughput rate the ISL2671286 power consumption is reduced slightly at lower conversion rates. figure 29 shows the typical power consumption over a wide range of throughput rates. serial digital interface the ISL2671286 communicates usin g a 3-wire serial interface. dclock synchronizes the data transfer, with each bit transmitted on the falling dclock edge and captured on the rising dclock edge in the receiving system. a falling cs /shdn initiates data transfer, as shown in figure 3. after cs /shdn falls, the second dclock pulse enables dout. after one null bit, the a/d conversion result is output on the dout line. bringing cs /shdn high resets the ISL2671286 for the next data exchange. figure 3 shows a detailed timing diagram for the se rial interface. the serial clock provides the conversion clock and controls the transfer of data during conversion. cs /shdn initiates the conversion process and frames the data transfer. the falling edge of cs /shdn puts the track-and-hold into hold mode and takes the bus out of three-state. the analog input is sampled and the conversion initiated at this point. the conversion result from the ISL2671286 is provided on dout output as a serial data stream. the bits are clocked out on the falling of the sclk input. the output coding is two?s complement. applications information analog input filtering a low-pass, anti-alias filter is recommended to optimize performance, as shown in figure 31. the capacitive input switching currents are averaged into a net dc current by c filt . it is recommended that a high-quality capacitor with low voltage and temperature coefficients, such as c0g/np0, be used. a small series resistance value mi nimizes voltage drops across the resistor. reduced reference operation the ISL2671286 exhibits good linearity and gain over a wide range of reference voltages (see figures 10 and 11). when operating at low values of vref, offset errors and noise must be considered because of the reduced lsb size. input errors can have a larger impact on performance when operating the adc with a reduced reference voltage, since lsb size is proportional to vref. fi gure 8 shows how the offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 100v is 0.082 lsb with a 5v reference. if vref is reduced to 1v, the same 100v offset is 0.41 lsb, and it increases to 2.05 lsb with a 0.2v reference. the offset can be corrected digitally after conversion, or an opposing bias can be applied to the ?in pin (within the allowable range according to the ?electrical specifications?). similarly, total input referred noise appears as a larger fraction of an lsb when operating at reduced vref values. attention should be paid to the output noise of the driving amplifier, and proper filtering should be applied to li mit the noise that aliases in the nyquist zone. averaging multiple readings can improve performance if the application conditions allow. grounding and layout the printed circuit board that ho uses the ISL2671286 should be designed so that the analog and digital sections are separated figure 29. supply current vs sample rate 1 10 100 1000 0.1 1.0 10 100 sample rate (khz) supply current (a) t a = 25c v cc = +5v v ref = +5v f clk = 16 x f sample figure 30. shutdown current vs sample rate 0 1 2 3 4 5 6 0.1 1.0 10 100 sample rate (khz) t a = 25c v cc = +5v v ref = +5v f clk = 16 x f sample csb = low (gnd) csb = high (v cc ) supply current (a) figure 31. input filtering ISL2671286 +in ? in v in c filt r filt i dc
ISL2671286 13 fn7863.0 november 1, 2011 and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes because it gives the best shielding. digital and analog ground planes should be joined in only one place, and the connection should be a star ground point established as close to the gnd pin on the ISL2671286 as possible. avoid running digital lines under the device, as this couples noise on to the die. the analog ground plane should be allowed to run under the ISL2671286 to avoid noise coupling. power supply lines to the device should use as large a trace as possible, to provide low impedance paths and to reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. clock signals should neve r run near analog inputs. avoid crossover of digital and analog si gnals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by fa r the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best performance from these decoupling components, they must be placed as close as possible to the device. terminology signal-to-(noise + dist ortion) ratio (sinad) sinad is the measured ratio of si gnal-to-(noise + distortion) at the output of the adc. the sign al is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process: the more le vels, the smaller the quantization noise. the theoretical signal-to-(n oise + distortion) ratio for an ideal n-bit converter with a sine wave input is given in equation 1: thus, for a 12-bit converter, the ratio is 74db and for a 10-bit converter is 62db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. fo r the ISL2671286, it is defined as shown in equation 2: where v 1 i s the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonic. peak harmonic or spurious noise (sfdr) peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. also referred to as spurious free dynamic range (sfdr), the value of this specification normally is determined by the largest harmonic in the spectrum. for adcs in which the harmonics are buried in the noise floor, however, sfdr is a noise peak. small-signal bandwidth small-signal bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a signal whose peak-to-peak amplitude spans no more than 10% of the full-scale input range. integral nonlinearity (inl) integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero-code error zero-code error is the deviation of the first code transition (000...000 to 000...001) from an ideal ? lsb step. gain error gain error is the deviation of th e full-scale input (111...111) from the ideal span (i.e., +vref ? 1lsb) after the zero code error has been adjusted out. track-and-hold acquisition time track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) power supply rejection ratio is th e ratio of the power in the adc output at full-scale frequency, f, to adc +vcc supply of frequency f s (equation 3). the frequency of this input varies from 1khz to 1mhz. pf is the power at frequency f in the adc output; pfs is the power at frequency f s in the adc output. signal-to-(noise + distortion) 6.02 n 1.76 + () db = (eq. 1) (eq. 2) thd db () 20 v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 ++++ v 1 2 ------------------------------------------------------------------- - log = (eq. 3) psrr db () 10 pf pfs ? () log =
ISL2671286 14 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7863.0 november 1, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL2671286 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change 11/1/2011 fn7863.0 initial release
ISL2671286 15 fn7863.0 november 1, 2011 package outline drawing m8.15 8 lead narrow body small outline plastic package rev 3, 3/11 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m-1982. 2. package length does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. package width does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 5. terminal numbers are shown for reference only. 6. the lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. controlling dimension: millimeter. co nverted inch dimensions are not necessarily exact. 8. this outline conforms to jedec publication ms-012-aa issue c. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 0.25(0.010) 0.10(0.004) 0.51(0.020) 0.33(0.013) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 1 2 3 4 5 6 7 8 typical recommended land pattern 2.20 (0.087) 0.60 (0.023)

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